Methods and circuits for performing margining tests in the presence of a decision feedback equalizer

ABSTRACT

Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.

BACKGROUND

[0001] Signal distortion limits the sensitivity and bandwidth of anycommunication system. A form of distortion commonly referred to as“intersymbol interference” (ISI) is particularly problematic and ismanifested in the temporal spreading and consequent overlapping ofindividual pulses, or “symbols.” Severe ISI prevents receivers fromdistinguishing symbols and consequently disrupts the integrity ofreceived signals.

[0002]FIG. 1 (prior art) depicts a conventional receiver 100, which isused here to illustrate the ISI problem and a corresponding solution.Receiver 100 includes a data sampler 105 and a feedback circuit 110.Sampler 105 includes a differential amplifier 115 connected to adecision circuit 120. Decision circuit 120 periodically determines theprobable value of signal Din and, based on this determination, producesa corresponding output signal Dout.

[0003] Sampler 105 determines the probable value of signal Din bycomparing the input signal Din to a voltage reference Vref at a preciseinstant. Unfortunately, ISI depends partly on the received data pattern,so the voltage level used to express a given logic level varies withhistorical data patterns. For example, a series of logic zero signalsfollowed by a logic one signal produces different ISI than a series ofalternating ones and zeroes. Feedback circuit 110 addresses this problemusing a technique known as Decision Feedback Equalization (DFE), whichproduces a corrective feedback signal that is a function of historicaldata patterns.

[0004] DFE feedback circuit 110 includes a shift register 125 connectedto the inverting input of amplifier 115 via a resistor ladder circuit130. In operation, receiver 100 receives a series of data symbols on aninput terminal Din, the non-inverting input terminal of amplifier 115.The resulting output data Dout from sampler 105 is fed back to shiftregister 125, which stores the prior three output data bits. (As withother designations herein, Din and Dout refer to both signals and theircorresponding nodes; whether a given designation refers to a signal or anode will be clear from the context.)

[0005] Shift register 125 includes a number of delay elements, threeflip-flops D1-D3 in this example, that apply historical data bits to thereference voltage side of the differential amplifier 115 via respectiveresistors R1, R2, and R3. The value of each resistor is selected toprovide appropriate weight for the expected effect of the correspondinghistorical bit. In this example, the value of resistor R3 is highrelative to the value of resistor R1 because the effect of the olderdata (D3) is assumed to be smaller than the effect of the newer data(D1). For the same reason, the resistance of resistor R2 is between theresistors R1 and R3. Receiver 100 includes a relatively simple DFEcircuit for ease of illustration: practical DFE circuits may sample moreor fewer historical data values. For a more detailed discussion of anumber of receivers and DFE circuits, see U.S. Pat. No. 6,493,394 toTamura et al., issued Dec. 10, 2002, which is incorporated herein byreference.

[0006] The importance of accurate data reception motivates receivermanufacturers to characterize carefully their system's ability totolerate ISI and other types of noise. One such test, a so-called“margin” test, explores the range of voltage and timing values for whicha given receiver will properly recover input data.

[0007]FIG. 2 depicts a fictional eye pattern 200 representingdifferential input data to a conventional receiver. Eye pattern 200 isgraphed in two dimensions, voltage V and time T. The area of eye 205represents a range of reference voltages and timing parameters withinwhich the data represented by eye 205 will be captured. The degree towhich the voltage V and time T can vary without introducing an error istermed the “margin.”

[0008]FIGS. 3A through 3C depict three signal eyes 300, 305, and 310illustrating the effects of DFE on margins and margin testing. Referringfirst to FIG. 3A, eye 300 approximates the shape of eye 205 of FIG. 2and represents the margin of an illustrative receiver in the absence ofDFE. FIG. 3B represents the expanded margin of the same illustrativereceiver adapted to include DFE: the DFE reduces the receiver's ISI, andso extends the margins beyond the boundaries of eye 300. Increasing themargins advantageously reduces noise sensitivity and improves bit errorrates (BER).

[0009] In-system margin tests for a receiver are performed by monitoringreceiver output data (e.g., Dout in FIG. 1) while varying the referencevoltage and sample timing applied to the input waveform Din. Withreference to FIG. 2, such testing samples various combinations ofvoltage and time to probe the boundaries of eye 205, the boundariesbeing indicated when the output data does not match the input data.Margin tests thus require the receipt of erroneous data to identifysignal margins. Zerbe et al. detail a number of margin tests in “Methodand Apparatus for Evaluating and Optimizing a Signaling System,” U.S.patent application Ser. No. 09/776,550, which is incorporated herein byreference.

[0010] A difficulty arises when determining the margins of DFE-equippedreceivers. While feeding back prior data bits increases the margin (FIG.3B), the effect is just the opposite if the feedback data is erroneous.Erroneous feedback emphasizes the ISI and consequently reduces themargin, as shown in FIG. 3C. The margin of a DFE-equipped receiver thuscollapses when a margin test begins to probe the limits of the testsignal (e.g., the boundaries of eye 205).

[0011] The incompatible requirements of erroneous data for the margintest and correct data for the DFE thus impede margin testing. There istherefore a need for improved means of margin testing DFE-equippedreceivers.

SUMMARY

[0012] The present invention is directed to methods and circuits formargin testing receivers equipped with Decision Feedback Equalization(DFE) or forms of feedback that employ historical data to reduceinter-symbol interference (ISI). In accordance with one embodiment, aknown input data stream is transmitted to a high-speed serial receiverwith DFE. The receiver injects a copy of the known input data stream(i.e., the “expected data”) into the feedback path irrespective ofwhether the receiver correctly interprets the input data. The marginsare therefore maintained in the presence of receiver errors, allowingin-system margin tests to probe the margin boundaries without collapsingthe margin. Receivers in accordance with some embodiments include localsources of expected data; other embodiments derive the expected datafrom test data applied to the receiver.

[0013] This summary does not limit the invention, which is insteaddefined by the allowed claims.

BRIEF DESCRIPTION OF THE FIGURES

[0014]FIG. 1 (prior art) depicts a conventional digital receiver 100.

[0015]FIG. 2 depicts a fictional eye pattern 200 representingdifferential input data to a conventional receiver.

[0016]FIGS. 3A through 3C depict three signal eyes 300, 305, and 310illustrating the effects of DFE on margins and margin testing.

[0017]FIG. 4 depicts a communication system 400, including aconventional transmitter 402 connected to a DFE-equipped receiver 403adapted in accordance with one embodiment.

[0018]FIG. 5 depicts a DFE-equipped receiver 500 adapted in accordancewith an embodiment to include improved means of margin testing.

[0019]FIG. 6 depicts a receiver 600 in accordance with anotherembodiment.

[0020]FIG. 7 depicts a receiver 700 in accordance with yet anotherembodiment.

[0021]FIG. 8 depicts an embodiment of a buffer 800, which may be used asone of buffers 745 in weighting circuit 735 of FIG. 7.

DETAILED DESCRIPTION

[0022]FIG. 4 depicts a communication system 400, including aconventional transmitter 402 connected to a receiver 403 equipped withDecision Feedback Equalization (DFE). In a normal operational mode,receiver 403 samples an input data stream from transmitter 402. Thesampled data provides DFE feedback to reduce intersymbol interference(ISA). In a margin-test mode, receiver 403 samples a known input datastream using ranges of sample timing and reference voltages. To preventa collapse of the margins, the DFE feedback path disregards thepotentially erroneous sampled data in favor of an identical version ofthe known input data stream. In-system margin tests can therefore probethe margin without collapsing the margin limits.

[0023] Receiver 403 conventionally includes a sampler 405, an optionalclock-data recovery (CDR) circuit 410, and a DFE circuit 415. Duringnormal operation, receiver 403 receives a data stream (e.g., a series ofdata symbols) on sampler input terminal Din. Sampler 405 samples thedata stream using a recovered clock RCK from CDR circuit 410 andproduces the resulting sampled data stream on a sampler output terminalDout. DFE circuit 415 stores a plurality of prior data samples and usesthese to condition the input data in the manner discussed above inconnection with FIG. 1. In addition to the conventional components,receiver 403 includes a multiplexer 420, an expected-data source 425,and some comparison logic 430, in this case an exclusive OR gate.

[0024] During normal operation, a test control signal T to multiplexer420 is set to a logic zero to connect the output data Dout to the inputof DFE 415. Thus configured, receiver 403 acts as a conventionalDFE-equipped receiver. In a margin-test mode, however, select signal Tis set to a logic one so as to convey an expected data stream from datasource 425 to the input of DFE 415. Transmitter 402 then supplies knowntest data on terminal Din while the expected data is applied to DFE 425.The expected data is an identical, time-shifted version of the knowndata applied to input terminal Din, so DFE 415 produces the correctfeedback without regard to the output signal Dout. In essence,multiplexer 420 provides the feedback path with a first input terminalfor sampled output data in the operational mode and with a second inputterminal for expected data in the margin-test mode.

[0025] The repeated reference herein to “terminal” Din, as opposed tothe plural form “terminals,” is for brevity. Receivers may include morethan one data-input terminal, such as those that rely upon differentialsignaling. Likewise, other clock, reference, and signal paths notedherein can be single-ended, differential, etc., as will be evident tothose of skill in the art. The preferred manner in which particular testcircuits and methods are adapted for use with a given receiver willdepend, in part, on the receiver architecture.

[0026] A voltage control signal CV on a like-named sampler inputterminal alters the reference voltage used by sampler 405 to sampleinput data. A clock control signal CC to CDR circuit 410 modifies thetiming of recovered clock signal RCK. Control signals CV and CC are usedin margin testing to explore the voltage and timing margins of receiver403. When the margin tests reach the margin limits, and thus introduceerrors in output signal Dout, expected-data source 425 continues toprovide the correct DFE feedback signal and consequently prevents themargins from collapsing in response to the errors. Comparison circuit430 monitors the sampled-data series for errors by comparing the outputdata with the expected data from expected-data source 425. In the eventof a mismatch, comparison circuit 430 produces a logic one error signalERR. A sequential storage element (not shown) captures any error signal.Receiver 403 thus facilitates margin testing of DFE-equipped receiverswithout collapsing the margin of interest. (Error signal ERR is notmonitored in the operational mode.)

[0027] Expected-data source 425 produces the same data as expected oninput terminal Din. Source 425 can be a register in which is previouslystored a known data pattern to be provided during margin testing. Source425 might also be a register that goes through an expected sequence ofdata, such as a counter or a linear-feedback shift register (LFSR).Regardless of the source, the expected data presents the expected outputdata, appropriately timed, to the input of the feedback circuit DFE 415.

[0028]FIG. 5 depicts a receiver circuit 500 in accordance with anotherembodiment. Receiver 500 is similar in some ways to receiver 403 of FIG.4, like-numbered elements being the same. Receiver 500 is extended toinclude a second sampler 505 that is substantially identical to, andconsequently mimics the behavior of, sampler 405. The margin tests areperformed on replica sampler 505 so that margin-testing circuitry haslittle or no impact on the performance of receiver 500 in theoperational mode.

[0029] Receiver 500 includes a multiplexer 510 connected to a shiftregister 515. A modified clock and data recovery circuit CDR 520controls the timing of both samplers 505 and 405. The timing controlterminal is omitted for brevity.

[0030] Prior to a margin test, test signal T is set to logic zero andthe storage elements within register 515 are loaded with anexpected-data sequence. Then, in the test mode, test terminal T is setto logic one so that shift register 515 feeds its output back to itsinput via multiplexer 510. To perform a margin test, sampler 505 samplesinput data Din. Comparison circuit 430 compares the resulting sampleswith the expected-data sequence provided by the first storage element inregister 515. Any difference between the data sampled by the replicasampler 505 and the expected sequence from register 515 inducescomparison circuit 430 to produce a logic one error signal on line ERR.Clocking circuitry, e.g. within CDR 520, can be adapted to controlseparately the recovered clock signals RCK1 and RCK2.

[0031]FIG. 6 depicts a receiver 600 in accordance with anotherembodiment. Receiver 600 is similar to the conventional receiver 100 ofFIG. 1, but is modified to support improved margin testing.

[0032] Receiver 600 includes a sampler 602 that, like sampler 105 ofFIG. 1, includes a differential amplifier 115 and a decision circuit120. Although not shown, sampler 602 includes conventional means ofadjusting the reference voltage and timing to support margin testing.DFE of receiver 600 performs conventionally in the operational mode andprovides expected data in the margin-test mode.

[0033] Receiver 600 includes a multiplexer 605, a comparison circuit610, and a dual-mode register 615, multiplexer 605 conveys output signalDout to register 615 in the operational mode. Thus configured, receiver600 functions analogously to receiver 100 of FIG. 1. That is, register615 shifts in the output data Dout and employs three bits of historicdata to provide ISI-minimizing feedback to sampler 602.

[0034] During margin testing, test signal T is set to logic one. In thatcase, multiplexer 605 provides the output of an XOR gate 620 to theinput of register 615. The inclusion of XOR gate 620 and the paththrough multiplexer 605 converts register 615 into a linear-feedbackshift register (LFSR) that provides a pseudo-random but deterministicsequence of bits to both the input of register 615 and XOR gate 610.Also during the margin test, the same pseudo-random sequence produced byregister 615 is provided on input terminal Din. This test sequence isapplied one clock cycle ahead of the expected data from register 615, sothe DFE will reflect the appropriate data regardless of whether outputdata Dout is correct. The timing and reference voltage of sampler 602can therefore be adjusted while monitoring output data Dout for errorswithout fear of collapsing the margin limits. Comparison circuit 610, anexclusive OR gate in this example, flags any mismatches between theoutput data and the expected data to identify errors.

[0035] In the example of FIG. 6, the pseudo-random sequence of test bitsapplied to input terminal Din is assumed to come from an externalsource, such as a conventional tester. The disclosed embodiments canalso be adapted to support built-in self test (BIST) or in-systemtesting. For example, a linked transmitter/receiver pair adapted inaccordance with one embodiment can margin test the intervening link. Inother embodiments, receiver 600 is modified so that register 615 oranother on-chip source provides the input test sequence. In someembodiments, register 615 is extended to include additional storageelements to produce more complex pseudo-random bit sequences. In suchcases, the number of outputs from register 615 to the input of sampler602 can be the same as or different from the number of storage elementsemployed by the LFSR. For additional details regarding LFSRs, see“What's an LFSR,” document no. SCTA036A from Texas Instruments™(December 1996) and the Xilinx™ application note entitled “EfficientShift Registers, LFSR Counters, and Long Pseudo-Random SequenceGenerators,” by Peter Alfke, XAPP 052, 7 Jul. 1996 (Version 1.1), bothof which are incorporated herein by reference.

[0036]FIG. 7 depicts a receiver 700 in accordance with yet anotherembodiment. FIG. 7 includes a number of elements that are incidental toinventive margin-testing circuitry, and so are only touched upon brieflyhere. The main components of the margin-testing circuitry arehighlighted using bold outlines to distinguish them from incidentalfeatures. The emphasized components include a pair of conventionalsamplers 705 and 710 receiving input data on the same input terminal,Din, a pair of multiplexers 715 and 720, a pair of shift registers 725and 730, and a data-weighting circuit 735.

[0037] In the operational mode, multiplexers 715 and 720 both selecttheir zero input. The input data Din captured by samplers 705 and 710 isthus conveyed to respective shift registers 725 and 730. The data inshift register 730 is the output data DATA of receiver 700, and is fedback to weighting circuit 735. For equalization feedback, all or asubset of the bits stored in the plurality of storage elements that makeup shift register 730 are provided to weighting circuit 735. In oneembodiment, shift registers 725 and 730 each store twenty bits. Ofthese, five bits from register 730 are conveyed to weighting circuit735. The selected bits and their associated weighting are optimized fora given receiver. For a detailed discussion of methods and circuits forperforming such optimization, see U.S. application Ser. No. 10/195,129entitled “Selectable-Tap Equalizer,” by Zerbe et al., filed Jul. 12,2002, which is incorporated herein by reference. The details of thatreference pertain to the optimization of a number of novel receivers.The margining methods and circuits disclosed herein may be of use in anysystems that employ historical data to reduce ISI.

[0038] Weighting circuit 735 produces a weighted sum of a plurality ofhistorical bits and applies this sum to input terminal Din. This is thesame general function provided by the ladder circuit of FIG. 1, thoughthe manner in which these weighting circuits performs this functiondiffers significantly.

[0039] Weighting circuit 735 includes five amplifiers 745[0:4], each ofwhich receives a bit from shift register 730. A weight-reference circuit750 provides each amplifier 745 with a reference signal (e.g., aconstant current) that determines the weight given to the associatedbit. The output terminals of amplifiers 745[0:4] are connected to inputterminal Din to provide a weighted sum of five historical data valuesfrom shift register 730. A current-controlled embodiment of an amplifier745[i] is detailed below in connection with FIG. 8.

[0040] In the margin-test mode, each of multiplexers 715 and 720 selectsits “one” input. The output of sampler 705 is thus conveyed to shiftregister 730 and the output of sampler 710 is conveyed to shift register725. Recall that a function of the margin-test mode is to provideexpected data to the input of the DFE circuitry. In this case, theexpected data is the input data sampled by sampler 705 and captured inshift register 730. A voltage-control signal CV2 and timing controlsignal CT2 allow a tester or test personnel to alter the referencevoltage and received clock RCK2 as necessary to probe the marginboundaries for sampler 710. Similar control signals CV1 and CT1 affordsimilar control over sampler 705 and are set to appropriate levels toensure sampler 705 correctly captures the input data.

[0041] During a margin test, erroneous bits from sampler 710 are storedin shift register 725. Comparison circuit 755 will therefore produce alogic-one error signal on line ERR. In this embodiment, it is notnecessary to store expected data in advance or to provide a dedicatedsource of expected data. Instead, the expected data is derived frominput data on terminal Din. The sampler used to produce output data inthe operational mode, sampler 710, is the same register subjected to themargin test. Testing the receive circuitry, as opposed to a replica, isadvantageous because it provides a more accurate reading of the actualreceive-circuitry performance. Also important, sampler 705 can bemargined in a normal operating mode, assuming that it has independenttiming and voltage control relative to sampler 710.

[0042] Receiver 700 of FIG. 7 is an equalizing receiver that generatesreceive and equalization clock signals. The following discussionoutlines various features of receiver 700. For a more detaileddiscussion of similar receivers, see the above-incorporated applicationto Zerbe et al.

[0043] In addition to the components discussed above in relation to themargin-testing methods and circuits, receiver 700 includes a CDR circuit755 and an equalizer clock generator 759. Samplers 705 and 710 sampleincoming data signal Din in response to respective receive-clock signalsRCK1 and RCK2, both the which are derived from a reference clock RCLK.The samples taken by sampler 710 are shifted into register 730, wherethey are stored for parallel output via output bus DATA to someapplication logic (not shown) and to CDR circuit 755.

[0044] Receive clock signal RCLK includes multiple component clocksignals, including a data clock signal and its complement for capturingeven and odd phase data samples, and an edge clock signal and acomplement edge clock signal for capturing edge samples (i.e.,transitions of the data signal between successive data eyes). The dataand edge samples are shifted into shift registers 725 and 730. Samplesin register 730 and then supplied as parallel words (i.e., a data wordand an edge word) to a phase control circuit 761 within CDR circuit 755.Phase control circuit 761 compares adjacent data samples (i.e.,successively received data samples) within a data word to determine whendata signal transitions have taken place, then compares an interveningedge sample with the preceding data sample (or succeeding data sample)to determine whether the edge sample matches the preceding data sampleor succeeding data sample. If the edge sample matches the data samplethat precedes the data signal transition, then the edge clock is deemedto be early relative to the data signal transition. Conversely, if theedge sample matches the data sample that succeeds the data signaltransition, then the edge clock is deemed to be late relative to thedata signal transition. Depending on whether a majority of suchearly/late determinations indicate an early or late edge clock (i.e.,there are multiple such determinations due to the fact that each edgeword/data word pair includes a sequence of edge and data samples), phasecontrol circuit 761 asserts an up signal (UP) or down signal (DN). Ifthere is no early/late majority, neither the up signal nor the downsignal is asserted.

[0045] Each of a pair of mix logic circuits 763 and 765 receives a setof phase vectors 767 (i.e., clock signals) from a reference loop circuit769 and respective timing control signals CT1 and CT2 as noted above.The phase vectors have incrementally offset phase angles within a cycleof a reference clock signal. For example, in one embodiment thereference loop outputs a set of eight phase vectors that are offset fromone another by 45 degrees (i.e., choosing an arbitrary one of the phasevectors to have a zero degree angle, the remaining seven phase vectorshave phase angles of 45, 90, 135, 180, 225, 270 and 315 degrees). Mixlogic circuits 763 and 765 maintain respective phase count values, eachof which includes a vector select component to select a phase-adjacentpair of the phase vectors (i.e., phase vectors that bound a phase angleequal to 360°/N, where N is the total number of phase vectors), and aninterpolation component (INT). The interpolation component INT and apair of phase vectors V1 and V2 are conveyed from each of mix logiccircuits 763 and 765 to respective receive-clock mixer circuits 770 and772. Mixer circuits 770 and 772 mix their respective pairs of phasevectors according to the interpolation component INT to generatecomplementary edge clock signals and complementary data clock signalsthat collectively constitute first and second receive-clock signals RCK1and RCK2, which serve as input clocks for samplers 705 and 710,respectively. Timing control signals CT1 and CT2 facilitate independentcontrol of the timing of clock signals RCK1 and RCK2.

[0046] Mix logic circuit 765 increments and decrements the phase countvalue in response to assertion of the up and down signals, respectively,thereby shifting the interpolation of the selected pair of phase vectors(or, if a phase vector boundary is crossed, selecting a new pair ofphase vectors) to retard or advance incrementally the phase of thereceive clock signal. For example, when the phase control logic 761determines that the edge clock leads the data transition and asserts theup signal, mix logic 765 increments the phase count, therebyincrementing the interpolation component INT of the count and causingmixer 772 to incrementally increase the phase offset (retard the phase)of receive-clock signal RCK1. At some point, the phase control signaloutput begins to dither between assertion of the up signal and the downsignal, indicating that edge clock components of the receive clocksignal have become phase aligned with the edges in the incoming datasignal. Mix logic 763 and mixer 770 are analogous to mix logic 765 and772, but control the receive clock RCK1 to sampler 705. These redundantcircuits are provided so the receive-clock timing to samplers 705 and710 can be independently adjusted during margin testing.

[0047] The equalizer clock generator 759 receives the phase vectors 767from the reference loop 769 and includes mix logic 774 and an equalizerclock mixer 776, which collectively operate in the manner describedabove in connection with mix logic 765 and mixer 772. That is, mix logic774 maintains a phase count value that is incrementally adjusted up ordown in response to the up and down signals from the phase controlcircuit 761. The mix logic selects a phase-adjacent pair of phasevectors 767 based on a vector select component of the phase count. Themix logic then outputs the selected vectors (V1, V2) and interpolationcomponent of the phase count (INT) to the equalizer clock mixer 776.Clock mixer 776 mixes the selected vectors in accordance with theinterpolation component of the phase count to generate the equalizerclock signal EQCLK. The equalizer clock signal, which may includecomplementary component clock signals, is provided to weighting circuit735 (or other type of equalization circuit) to time the output ofequalizing signals onto data input terminal Din.

[0048]FIG. 8 depicts an embodiment of a buffer 800 that may be used asone of buffers 745 in weighting circuit 735 of FIG. 7 in an embodimentin which the data input Din is a two-terminal port receivingdifferential input signals Din and /Din. Clock signal EQCLK is also adifferential signal EQCLK and /EQCLK in this embodiment.

[0049] Buffer 800 receives one of five differential feedback signals(EQDin[i] and /EQDin[i]) and the differential clock signal (EQCLK and/EQCLK) from mixer 776. Reference circuit 750 provides a referencevoltage EQWi that determines the current through buffer 745, andconsequently the relative weight of the selected feedback data bit.

[0050] The above-described embodiments are adapted for use in receiversof various types. The embodiment of FIG. 6, for example, is applied to areceiver adapted to receive single-ended input signals, while theembodiments of FIGS. 7 and 8 are applied to receivers adapted to receivecomplementary signals. These examples are not limiting, as these andother embodiments can be applied to receivers adapted to communicatesignals in any of a number of communication schemes, includingpulse-amplitude modulated (PAM) signals (e.g., 2-PAM and 4-PAM), whichmay be used in some embodiments to provide increased data rates.

[0051] While the present invention has been described in connection withspecific embodiments, variations of these embodiments will be obvious tothose of ordinary skill in the art. Moreover, unless otherwise defined,terminals, lines, conductors, and traces that carry a given signal fallunder the umbrella term “node.” In general, the choice of a givendescription of a circuit node is a matter of style, and is not limiting.Likewise, the term “connected” is not limiting unless otherwise defined.Some components are shown directly connected to one another while othersare shown connected via intermediate components. In each instance, themethod of interconnection establishes some desired electricalcommunication between two or more circuit nodes, or terminals. Suchcommunication may often be accomplished using a number of circuitconfigurations, as will be understood by those of skill in the art.Furthermore, only those claims specifically reciting “means for” or“step for” should be construed in the manner required under the sixthparagraph of 35 U.S.C. section 112. Therefore, the spirit and scope ofthe appended claims should not be limited to the foregoing description.

What is claimed is:
 1. A receiver comprising: a. a sampler having: i. aplurality of sampler input terminals, including at least one samplerdata terminal adapted to receive an input data stream and at least onesampler reference terminal; and ii. at least one sampler output terminaladapted to produce a sampled data stream; b. a feedback circuit having:i. a plurality of delay elements connected to the sampler outputterminal, each delay element adapted to provide at least one historicalbit from the sampled data stream; and ii. a plurality of data-weightingcircuits, each data-weighting circuit connected between one of theplurality of delay elements and at least one of the plurality of samplerinput terminals and adapted to provide a weighted feedback to thesampler based on the at least one historical bit from the correspondingdelay element; and c. a multiplexer having: i. a first multiplexer inputterminal connected to the at least one sampler output terminal; ii. asecond multiplexer input terminal connected to a source of expecteddata; and iii. a multiplexer output terminal connected to at least oneof the sampler input terminals and adapted to provide alternatively oneof the sampled data stream and the expected data.
 2. The receiver ofclaim 1, further comprising a comparison circuit adapted to compare thesampled data stream with the expected data.
 3. The receiver of claim 1,wherein the source of expected data comprises a register.
 4. Thereceiver of claim 3, wherein the source of expected data comprises ashift register.
 5. The receiver of claim 3, wherein the source ofexpected data derives the expected data from the input data stream.
 6. Areceiver comprising: a. a sampler having: i. at least one sampler inputterminal receiving a series of data symbols; and ii. at least onesampler output terminal producing a sampled data stream; b. anexpected-data node providing expected data; and c. a feedback circuitincluding: i. a first feedback-circuit input terminal connected to thesampler output terminal; and ii. a second feedback-circuit inputterminal connected to the expected-data node.
 7. The receiver of claim6, wherein the at least one sampler input terminal includes first andsecond complementary sampler input terminals, and wherein the feedbackcircuit further includes a feedback-circuit output terminal connected toat least one of the first and second complementary sampler inputterminals.
 8. The receiver of claim 6, the feedback circuit furtherincluding a shift register, the shift register including a plurality ofstorage elements and a shift-register input terminal connected to thesampler output terminal, the storage elements each storing a bit fromthe sampled data stream.
 9. The receiver of claim 8, the feedbackcircuit further including a plurality of data-weighting circuits, eachdata-weighting circuit connected between one of the plurality of storageelements and the at least one sampler input terminal.
 10. The receiverof claim 6, further comprising a comparison circuit comparing theexpected data with the sampled data stream.
 11. The receiver of claim 6,wherein the expected-data node comprises a second sampler.
 12. Thereceiver of claim 6, further comprising a second sampler having asecond-sampler input terminal receiving the series of data symbols. 13.The receiver of claim 6, wherein the series of data symbols areexpressed as a differential signal.
 14. A method of margin testing asignal receiver having a feedback circuit, the method comprising: a.sampling a series of input symbols to produce a sampled-data series; b.applying expected data to the feedback circuit; and c. monitoring thesampled-data series for errors while applying the expected data to thefeedback circuit.
 15. The method of claim 14, wherein the monitoringcomprises comparing the sampled-data series with the expected data. 16.The method of claim 14, further comprising deriving the expected datafrom the series of input signals.
 17. A communication system comprising:a. a transmitter adapted to transmit a series of data symbols; and b. areceiver including: i. a sampler having: 1) at least one sampler inputterminal adapted to receive a series of data symbols; and 2) at leastone sampler output terminal adapted to produce a sampled data stream;ii. a feedback circuit including: 1) a first feedback-circuit inputterminal connected to the sampler output terminal; and 2) a secondfeedback-circuit input terminal adapted to receive expected data. 18.The communication system of claim 17, wherein the receiver furtherincludes an expected-data source adapted to provide the expected data.19. The communication system of claim 18, wherein the expected-datasource generates the expected data.
 20. The communication system ofclaim 18, wherein the expected-data source receives the expected datafrom the transmitter.
 21. The communication system of claim 17, whereinthe series of data symbols is differential.
 22. A receiver having afeedback equalization path, the receiver comprising: d. a samplerhaving: i. at least one sampler input terminal adapted to receive aseries of data symbols; and ii. at least one sampler output terminaladapted to produce a sampled data stream; e. an expected-data nodeadapted to provide expected data; and f. a feedback circuit including:i. a first feedback-circuit input terminal connected to the sampleroutput terminal; and ii. a second feedback-circuit input terminalconnected to the expected-data node.
 23. The receiver of claim 22,wherein the at least one sampler input terminal includes first andsecond complementary sampler input terminals, and wherein the feedbackcircuit further includes a feedback-circuit output terminal connected toat least one of the first and second complementary sampler inputterminals.
 24. The receiver of claim 22, the feedback circuit furtherincluding a shift register, the shift register including a plurality ofstorage elements and a shift-register input terminal connected to thesampler output terminal, the storage elements each adapted to store abit from the sampled data stream.
 25. The receiver of claim 24, thefeedback circuit further including a plurality of data-weightingcircuits, each data-weighting circuit connected between one of theplurality of storage elements and the at least one sampler inputterminal.
 26. The receiver of claim 22, further comprising a comparisoncircuit adapted to compare the expected data with the sampled datastream.
 27. The receiver of claim 22, wherein the expected-data nodecomprises a second sampler.
 28. The receiver of claim 22, furthercomprising a second sampler having a second-sampler input terminaladapted to receive the series of data symbols.
 29. The receiver of claim22, wherein the series of data symbols are expressed as a differentialsignal.
 30. A receiver having a feedback path, the receiver comprising:a. means for sampling a series of input symbols to produce asampled-data series; b. a source of an expected-data series; and c.means for alternatively applying the sampled-data series or theexpected-data series to the feedback path.
 31. The receiver of claim 30,further comprising a means for comparing the sampled data series withthe expected-data series while applying the expected-data series to thefeedback path.